Translators | MC100EPT24

トランスレータ、LVTTL / LVCMOS から差動 LVECL へ

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製品

Overview

MC100EPT24 は、LVTTL/LVCMOS から差動 LVECL へのトランスレータです。LVECL レベルと LVTTL/LVCMOS レベルが使用されるため、必要なのは -3.3 V、+3.3V とグランドです。小型アウトライン 8 リード SOIC パッケージとシングル・ゲート EPT24 が特徴で、スペース、性能、および低電力が重要とされるアプリケーションに最適です。

  • Level Translator

  • 350ps Typical Propagation Delay
  • Maximum Frequency > 1.0GHz
  • The 100 Series Contains Temperature Compensation
  • Operating Range: VCC= 3.0 V to 3.6 V; VEE= -3.6 V to -3.0 V; GND = 0 V
  • PNP LVTTL Inputs for Minimal Loading
  • Q Output will default HIGH with inputs open
  • Pb-Free Packages are Available

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Product services, tools and other useful resources related to MC100EPT24

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製品:

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CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

Channels

Input Level

Output Level

VCC Typ (V)

fMax Typ (MHz)

tpd Typ (ns)

tR & tF Max (ps)

Reference Price

MC100EPT24DTG

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Active

CAD Model

Pb

A

H

P

TSSOP-8

948R-02

3

260

TUBE

100

1

TTL

ECL

3.3

1000

0.53

170

Price N/A

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MC100EPT24MNR4G

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CAD Model

Pb

A

H

P

DFN-8

506AA

1

260

REEL

1000

1

TTL

ECL

3.3

1000

0.53

170

Price N/A

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信頼性データ

Die Related Summary Data

Device: MC100EPT24DTG

Equivalent to wafer fab process: MOSAIC

製品技術

製品技術

等価デバイス時間

MTBF/MTTF (時間)

FITS

MOSAIC

0

476668904

207014408

4.83

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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