Latches & Registers | MC14015B

デュアル 4 ビット・スタティック・シフト・レジスタ

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MC14015B デュアル 4 ビット・スタティック・シフト・レジスタは、シングル・モノリシック構造の MOS P/N チャネル・エンハンスメントモード・デバイスによって構築されています。2 つの同等の独立した 4 ステート・シリアル入力/パラレル出力レジスタで構成されています。各レジスタには、独立したクロックおよびリセット入力があり、シングル・シリアルデータ入力を備えています。レジスタ・ステートは D マスタスレーブ・フリップフロップです。データは正方向にクロック遷移中ステージからステージへとシフトされます。各レジスタは、リセット・ラインに高レベルが適用されている時、クリアにできます。これらの相補 MOS シフト・レジスタの主な利用目的は、低電力消費および/または高ノイズ耐量が求められるバッファ・ストレージやシリアルからパラレルへの変換での使用です。

  • Diode Protection on All Inputs
  • Supply Voltage Range = 3.0 Vdc to 18 Vdc
  • Logic Edge-Clocked Flip-Flop Design - Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive goingedge of the clock pulse.
  • Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range.
  • Pb-Free Packages are Available*

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MC14015BDG

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CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

TUBE

48

N

Shift Register

2

3

18

250

2.25

$0.2561

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MC14015BDR2G

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CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

REEL

2500

N

Shift Register

2

3

18

250

2.25

$0.2561

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NLV14015BDR2G

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CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

REEL

2500

N

Shift Register

2

3

18

250

2.25

$0.2385

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信頼性データ

Die Related Summary Data

Device: MC14015BDG

Equivalent to wafer fab process: CMOS STD

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等価デバイス時間

MTBF/MTTF (時間)

FITS

CMOS STD

3

3597164517

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Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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