Phase / Frequency Detectors | MC100EP140

位相周波数ディテクタ、3.3 V、ECL

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MC100EP140 は、3 ステート位相周波数ディテクタで、ロックでの位相および周波数の差を最小限にする必要のある位相ロック・ループ・アプリケーションを意図しています。このパーツは完全差動ゲートで設計されているため、ノイズは回路全体で、特に高速時に低減されます。位相/周波数検出器 (PFD) の基本的な動作は、受け取る信号 (フィードバック) と設定リファレンス信号の「比較」です。リファレンス (R) 入力と VCO (V) 入力の周波数および/または位相が同じでない場合、差動 UP (U)/DOWN (D) 出力により求まるパルス列を引いて統合すると、VCO の制御のためのエラー電圧が求まります。デバイスは、小型アウトラインの表面実装 8 リード SOIC パッケージに収められています。EP140 の出力は 400 mV で、スイッチング時間よりも速く、帯域幅よりも大きくなります。+3.3 V システムでも使用できます。正しい動作させるため、R および FB 入力の入力エッジ・レートは 5 ns 未満にしてください。位相ロック・ループの動作およびアプリケーションの詳細については、AND8040 をご覧ください。

  • 500 ps Typical Propagation Delay
  • Maximum Frequency > 2.1 Ghz Typical
  • Fully Differential Internally
  • Advanced High Band Output Swing of 400 mV
  • Transfer Gain: 1.0 mV/Degree at 1.4 GHz, 1.2 mV/Degree at 1.0 GHz
  • Rise and Fall Time: 100 ps Typical
  • The 100 Series Contains Temperature Compensation
  • PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
  • Open Input Default State
  • Pb-Free Packages are Available

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Input Level

Output Level

VCC Typ (V)

Transfer Gain Typ (mV/degree)

CMRR Max (V)

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MC100EP140DR2G

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CAD Model

Pb

A

H

P

SOIC-8

751-07

1

260

REEL

2500

Y

ECL

ECL

3.3

1.2073

-

2000

0.475

0.2

200

Price N/A

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Die Related Summary Data

Device: MC100EP140DR2G

Equivalent to wafer fab process: MOSAIC

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製品技術

等価デバイス時間

MTBF/MTTF (時間)

FITS

MOSAIC

0

476668904

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Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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