Translators | MC100EPT622

トランスレータ、10 ビット LVTTL / LVCMOS から LVPECL へ

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Datasheet

製品

Overview

MC100EPT622 は、10 ビットの LVTTL/LVCMOS から LVPECL へのトランスレータです。 LVPECL (ポジティブ ECL) レベルが使用されるため、必要なのは +3.3 V とグランドのみです。 このデバイスには、LVPECL (ENPECL) または TTL / LVCMOS 入力 (ENTTL) のいずれかを受け入れることができる OR 接続のイネーブル入力があります。 入力を開いたままにすると、デフォルトで有効状態になります。 デバイスの設計は、チャネル間のスキューが低くなるように最適化されています。

  • 450 ps Typical Propogation Delay
  • Maximum Frequency > 1.5 GHz Typical
  • PECL Mode
  • Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
  • PNP LVTTL Inputs for Minimal Loading
  • Q Outputs Will Default HIGH with Inputs Open
  • The 100 Series Contains Temperature Compensation

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状態

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Channels

Input Level

Output Level

VCC Typ (V)

fMax Typ (MHz)

tpd Typ (ns)

tR & tF Max (ps)

Reference Price

MC100EPT622FAG

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CAD Model

Pb

A

H

P

LQFP-32

561AB

2

260

JTRAY

250

Y

10

TTL

ECL

3.3

1500

0.5

450

Price N/A

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MC100EPT622MNG

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CAD Model

Pb

A

H

P

QFN-32

488AM

1

260

TUBE

74

Y

10

TTL

ECL

3.3

1500

0.5

450

Price N/A

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Die Related Summary Data

Device: MC100EPT622FAG

Equivalent to wafer fab process: MOSAIC

製品技術

製品技術

等価デバイス時間

MTBF/MTTF (時間)

FITS

MOSAIC

0

476668904

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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